`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/12/20 13:58:32
// Design Name: 
// Module Name: PC
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module PC(
input clk,
    input rst,
    input ena,
    input [31:0] in,
    output [31:0] out
    );
    reg [31:0] register;
always @(negedge clk) begin
    if (ena)
    begin
        if(rst)
            register <= 32'h0040_0000;
        else
            register <= in;
    end
end
assign out  = rst ? 32'h0040_0000:(ena ? register :32'bz);
endmodule
